Technical Field
The present invention relates to semiconductor processing, and more particularly to methods and devices having a selective self-aligned contact etching process to minimize spacer erosion when forming source and drain contacts in devices with highly scaled gate pitches.
Description of the Related Art
One commonly employed technique for forming gate structures involves forming a line-type gate electrode structure above a layer of insulating material that is formed above an active region defined in a semiconductor substrate. Typically, the line-type gate electrode structures are formed by defining long parallel line-type structures, i.e., gate electrode structures that extend across multiple spaced-apart active regions and the isolation regions formed in the substrate between such spaced-apart active regions. At some point later in the process flow, these long, line-type gate electrode structures are subsequently “cut” by performing an etching process to define the gate electrodes having the desired length in the “gate-width” direction of the transistor device. This results in substantially rectangular shaped gate structures (when viewed from above) having the desired dimensions in the gate-length and gate width directions.
After the gate electrodes are patterned, a sidewall spacer is typically formed around the perimeter of the substantially rectangular shaped gate structure, i.e., the spacer is formed adjacent on all four side sidewalls (two sidewalls and two end surfaces) of each of the patterned gate electrodes. In some cases, a thin liner layer may be formed on the gate structure prior to forming the sidewall spacer. The sidewall spacer, in combination with the gate cap layer, function to protect the gate electrode structure in subsequent processing operations.
Unfortunately, as device dimensions have decreased and packing densities have increased, it is more likely that, when epi semiconductor material is formed in the source/drain regions, some of the epi material may undesirably form on the end surfaces of the polysilicon/amorphous silicon gate electrode. This may occur for several reasons. As noted above, after the gate structures are patterned, a sidewall spacer is formed around all four sides of the gate structure so as to, along with the gate cap layer, encapsulate and protect the gate electrode during subsequent processing operations. As packing densities have increased, the end-to-end spacing between two different gate electrode structures formed above two different active regions has decreased, thereby limiting the physical size, i.e., the width, of the protective sidewall spacers. Additionally, as the pitch between adjacent gate structures has decreased, the width of the protective sidewall spacers must also be decreased.
With respect to forming a sidewall spacer on a device, the duration of the etching process performed to form the spacer is typically increased to ensure that the layer of spacer material is completely cleared from the surfaces of the source/drain regions of the device. This over-etching also tends to reduce the width of the protective spacer. All of these factors and others tend to result in an undesirable thinning of the spacer, particularly at the corner of the gate electrode (the intersection between the side surfaces and the end surfaces of the gate electrode). It is not uncommon that, due to these factors and others, some portion of the polysilicon or amorphous silicon gate electrode material will be exposed at the time epi semiconductor material is formed in the source/drain regions of a planar or FinFET device. As a result, epi semiconductor material will undesirably form on the exposed portions of the gate electrode layer.
The extent and amount of undesirable epi semiconductor material formation will vary depending upon the particular application and the quality of the manufacturing processes used to manufacture the device. As a result of such undesirable and unpredictable epi formation, the resulting semiconductor devices and the integrated circuits including such devices may completely fail or operate at less than acceptable performance levels. Even after gate formation additional processing can still expose sidewall spacers to damage.
For example, current self-aligned contact (SAC) etches employ an oxide plasma dry etch which is selective to SiN to open source/drain (S/D) contact regions. Process margin for this type of process becomes smaller for small nodes (e.g., 7 nm), given the fact that SAC cap thickness may be reduced to only 25 nm, and spacer thickness may be only about 6 nm. This means even a 2 nm spacer thin down during the SAC etch will fail the minimum insulator rule of greater than >5 nm. Scaling of spacers and thinning due to scaling and erosion may result in increased risk of shorts between S/D regions and gate contacts.